Solder bumps are commonly used as an electrical connection between semiconductor chips and ceramic or organic substrates used to connect to the outside world. There are a variety of processes that can be used to connect the solder bump to the chip. In one such method, the finished chip is coated with one or more layers of protective insulator that protects the last level of metallization from mechanical handling damage and corrosion or oxidation. In order to connect the solder to the last metallization layer, a hole or “via” is formed in the protective insulation, and another conductive layer (under bump metallurgy) is deposited both into the via and over a region surrounding the via. The shape of the via is usually circular, and is centered with respect to the position of the solder bump. The last conductive layer has a dual purpose: (i) adhesion to the protective insulating layer, and (ii) formation of a good metallurgical bond with the solder.
Once the solder bumps are deposited onto the chip, the chip is then joined to the substrate by positioning the chip so that the solder bumps are aligned with the appropriate pads on the substrate, then heated in a furnace to above the melting point of the solder. However, the substrate has a much larger thermal expansion coefficient than the chip, which results in the substrate shrinking much more than the chip during cooling processes. This, in turn, causes shear stresses to develop on the solidified solder bumps, basically due to the thermal expansion mismatch between materials of the substrate and solder bump. This is even more exaggerated in technologies from 90 nm node and forward as such technologies employ advanced low-K and ultra-low-K back of the end line (BEOL) dielectrics, which are susceptible to delamination or cracking in response to the chip join thermal expansion coefficient stresses.
The shear stresses exert a rotating moment on the solder bumps that is perpendicular to the radial direction from the chip geographic center and the solder bump. The moment causes tensile stress to be concentrated at the outer edge of the solder bump where it comes into contact with the chip, and this tensile stress acts to pull the solder away from the surface of the chip. Accordingly, the relative displacement between the surface of the substrate and that of the chip is greater farther from the geographical center of the chip, such that the outermost solder bumps experience the largest shear stresses.
One way to alleviate the magnitude of the tensile stress at the edge of the via is to move the via edge farther away from the perimeter of the solder bump, either by decreasing the diameter of the via or increasing the diameter of the solder bump. However, increasing the diameter of the solder bump places restrictions on the bump placement, which directly competes with the drive to shrink the chip footprint. Decreasing the diameter of the via, on the other hand, begins to affect the current carrying ability of the joint, leading to earlier failure by solder bump electromigration. Thus, there are constraints on both the diameter of the via and that of the solder bump.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.